Informatics Publishing Limited

K. Palanisamy , K. Gireesan , V. Nagarajan , Maheshwar Hegde

Abstract

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A. Jagan ¹, V. Nagarajan ²

Affiliations
1 Anna University, Chennai, TamilNadu, IN
2 Department of Electronics and Communication Engineering, Adhiparasakthi Engineering College, Melmaruvathur, TamilNadu, IN

Abstract

The security level of Elliptic Curve Cryptography (ECC) system depends on the hardness of finding the discrete logarithm in a finite field, the curve parameters selection, bit length etc. Increased demand of security level insists the cryptosystem to prepare for higher key size. When the computational intensive ECC algorithm is implemented on field programmable gate arrays (FPGAs), the resource consumption is one of the key issues. The first objective of this paper is paving the steps in the design of typical ECC processor using ModelSim 5.7 and Xilinx 9.2i, and evaluating the performance measures viz. the hardware efficiency, the functionality efficiency, the area and power calculations. Secondly, this work implements an unique co-processor architecture for two different key sizes (160-bit and 256-bit) to figure out the absolute resource usage differences in term of power, area and speed. The bit length is the major parameter in key generation processes that deals with the time consuming operation scalar multiplication. ECC architectures over GF(2256) is designed with an efficient array multiplier and Montgomery scalar multiplication algorithm. The simulation result shows that with frequency 100MHz, the power consumption of ECC co-processor is 824mW and its occupies 27114 LUT’s and 1,64,292 gates. The architectures are implemented in Spartan3E family device XC3S1600E.

Keywords

Elliptic Curve Cryptography, Public Key Cryptography, Galois Fields, Key Length, Montgomery Scalar Multiplication Algorithm, Array Multiplier.

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V. Nagarajan ¹, V. Kannan ²

Affiliations
1 SASTRA University, Thanjavur, IN
2 Jeppiaar Institute of Technology, Sriperumpudur, Chennai, IN

Abstract

This paper identifies and resolves the weakness and limitation of existing Cellular Automata (CA)-based byte Error Correcting Code (ECC) and proposes an improved CA-based multi byte ECC which overcomes the identified weakness up to some extent. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed–Solomon (RS) Codes. In this paper we are designing the Cellular Automata (CA) based multi byte error correction architecture. Cellular Automata is established for developing bits and bytes Error Correcting Codes. This code is very much suited from Very Large Scale Integration design viewpoint and requires much less hardware and power for decoding. The existing CA based error correcting scheme explains only about the double byte error correction. But this paper explains the error correction possibilities even if more than two errors present.

Keywords

Cellular Automata, Error Correcting Code, Multi Byte ECC.

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V. Nagarajan ¹, V. Subapriya ²

Affiliations
1 Department of Electronics and Communication Engineering, Adhiparasakthi Engineering College, Melmaruvathur, IN
2 Department of Electronics and Communication Engineering, Adhiparasakthi Engineering College, Melmaruvathur, IN

Abstract

Carry select adder is mainly used in data processing processor to perform the fast arithmetic operations. The carry select adder divides the words to be added into blocks and forms two sums for each block in parallel, one with assumed carry in Cin of 0 and the other with Cin of 1. The basic carry select adder is not area efficient because it uses multiple pairs of Ripple Carry Adders. Ripple carry adder consists of number of full adder circuits, so it will occupy more area. Each full adder inputs a carry-in, which is the carry-out of the preceding adder. In this paper a modified carry select adder is designed for area efficient. This work uses the Binary to Excess -1 converter and Basic unit instead of Ripple carry adder with Cin=1 in regular carry select adder to achieve lower area. This is achieved by lesser number of logic gates than the n bit full adder in Ripple Carry Adder. The reduced number of gates of this work offers the great advantage in the reduction of area. The design proposed in this paper has been developed using modelsim. In the proposed design, linear carry select adder with binary to excess 1 converter occupies 35 LUT’s. The results analysis shows that the proposed carry select adder structure is better than the conventional carry select adder but it will increases the delay.

Keywords

Area Efficient, Carry Select Adder, Carry Propagation Delay.

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M. S. Swaminathan ¹, V. Nagarajan ¹

Affiliations
1 Indian Council of Agricultural Research, New Delhi, IN

Abstract

It is increasingly becoming evident from the food production data at global level, that the world food production is sufficient to feed the millions who are to-day malnourished, provided there is equitable distribution. It is in this context that the World Food Congress held in Rome in November 1974 passed a resolution for ensuring that by 1984 no child goes to bed hungry and no man's physical and mental capacity be allowed to be stunted due to malnutrition. This pious resolution gave hopes of international action for building up an International Food Security System. This talk of International Food Security System is not new since the concept is nearly 30 years old.

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V. Nagarajan

Abstract

This number of British Medical Bulletin has presented a comprehensive review on a wide range of problems posed by the undesirable effects of chemicals in our food and environment. The brief reviews presented by well-recognised experts in this field provide a proper perspective of the entire gamut of lurking dangers in foods consumed by common man. The seventy five page review has an admirable coverage of a variety of problems such as chemical hazards in the home, naturally occurring toxins, mycotoxins, problems through food processing and preservatives, heavy metals and water supplies, besides this, importance of analytical surveys, assessing hazards of exposure to low toxic substances, toxicological assessment of new foods and the crucial role of epidemiological studies in providing unambiguous answers in regard to the role of toxins in foods in the aetiology of some diseases in man or live-stock. There is a valuable compilation of available information on the geographic epidemiology of some of the known diseases arising from some food toxins and mycotoxins in man and live-stock.

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S. G. Srikantiah , V. Nagarajan

Abstract

Health hazards of pesticide residues in foods constitute an important public health problem. There is general agreement that malnutrition aggravates drug toxicity, and in countries where nutritional status of communities is unsatisfactory, it is important to have information on the interaction between pesticide toxicity and nutritional status.

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Y. G. Deosthale ¹, K. Visweswara Rao ¹, V. Nagarajan ¹, K. C. Pant ¹

Affiliations
1 National Institute of Nutrition, Indian Council of Medical Research, Jamai Osmania, Hyderabad-7, A. P., IN

Abstract

Bajra (Pennisetum typhoides) is an important millet crop in dry and semi-dry regions of northern and peninsular India. Both by acreage and grain production, it ranks fourth in cereal crops of India and forms a major staple food for large segments of the population. With the new strategy in agriculture and introduction of new high yielding bajra hybrids, it has now been possible to increase grain yields considerably.

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Y. G. Deosthale ¹, V. Nagarajan ¹, K. C. Pant ¹

Affiliations
1 National Institute of Nutrition, Indian Council of Medical Research, Jamai-Osntania, Hyderabad-7, IN

Abstract

The millet ragi (Eleusine Coracana) is an important staple foodgrain in central and southern parts of India. It is known to be a rich source of calcium, containing 0'3 to 0.4g per cent calcium as compared to other cereals which contain O.Ol to 0 04 g per cent.

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