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Computer Aided Partitioning for Design of Parallel Testable VLSI System


Affiliations
1 Department of Electronics and Communication Engineering, Arignar Anna Institute of Science and Technology, Sriperumbudur-602117, Tamilnadu, India
     

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Design automation is a challenge for tool designers, due to increasing complexity of building VLSI circuits with molecular and nano-scale precision. Recent emerging complex problems in the field of VLSI design can be easily solved through the divide and conquer approach using partitioning methods. Although, partitioning problem has major importance in the field of VLSI design automation, it is treated with a testing perspective in this paper. This facilitates to address the reliability and testability issues of VLSI systems during the early product development stages. An automated VLSI design tool for partitioning combinational CMOS circuits that can create parallel testable VLSI circuits is developed and discussed. This computer aided tool can optimize the design constraints of test time and hardware overhead for design-for-testability (DFT) by an exploration of the solution search space. After partitioning and optimization, a considerable reduction in the length of test vectors is obtained.

Keywords

Directed Acyclic Graph, Circuit Under Test, Linear Feedback Shift Register, Built in Logic Block Observer, Multiple Input Signature Analyzer.
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  • Computer Aided Partitioning for Design of Parallel Testable VLSI System

Abstract Views: 270  |  PDF Views: 4

Authors

M. R. Ezilarasan
Department of Electronics and Communication Engineering, Arignar Anna Institute of Science and Technology, Sriperumbudur-602117, Tamilnadu, India
D. Uthirapathi
Department of Electronics and Communication Engineering, Arignar Anna Institute of Science and Technology, Sriperumbudur-602117, Tamilnadu, India

Abstract


Design automation is a challenge for tool designers, due to increasing complexity of building VLSI circuits with molecular and nano-scale precision. Recent emerging complex problems in the field of VLSI design can be easily solved through the divide and conquer approach using partitioning methods. Although, partitioning problem has major importance in the field of VLSI design automation, it is treated with a testing perspective in this paper. This facilitates to address the reliability and testability issues of VLSI systems during the early product development stages. An automated VLSI design tool for partitioning combinational CMOS circuits that can create parallel testable VLSI circuits is developed and discussed. This computer aided tool can optimize the design constraints of test time and hardware overhead for design-for-testability (DFT) by an exploration of the solution search space. After partitioning and optimization, a considerable reduction in the length of test vectors is obtained.

Keywords


Directed Acyclic Graph, Circuit Under Test, Linear Feedback Shift Register, Built in Logic Block Observer, Multiple Input Signature Analyzer.



DOI: https://doi.org/10.36039/ciitaas%2F7%2F1%2F2015%2F106762.20-27