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Effect of CNTFET on Carry Skip Adder


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1 Sathyabama University, Chennai, Tamilnadu, India
     

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This paper enumerates the efficient design and analysis of a Carry Skip Adder using Full Adder cell. The Full Adder is designed using Stanford University CNTFET model and proposed 10nm CNTFET model. There are many issues facing while integrating more number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by considering the carbon nano tube have promising application in the field of electronics. The carbon nanotube is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage at 0.9V. The simulation results are presented and the analyses are compared with circuits designed using 32nm MOSFET. The comparison of results indicated that the proposed 10nm CNTFET based design is more efficient in power savings and speed.


Keywords

CNT, CNTFET, Full Adder Cell, Carry Skip Adder, Design Constraints and Circuit Simulation.
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  • Effect of CNTFET on Carry Skip Adder

Abstract Views: 258  |  PDF Views: 6

Authors

Sree Harsha Parimi
Sathyabama University, Chennai, Tamilnadu, India
S. Mukilan
Sathyabama University, Chennai, Tamilnadu, India
T. Ravi
Sathyabama University, Chennai, Tamilnadu, India

Abstract


This paper enumerates the efficient design and analysis of a Carry Skip Adder using Full Adder cell. The Full Adder is designed using Stanford University CNTFET model and proposed 10nm CNTFET model. There are many issues facing while integrating more number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by considering the carbon nano tube have promising application in the field of electronics. The carbon nanotube is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage at 0.9V. The simulation results are presented and the analyses are compared with circuits designed using 32nm MOSFET. The comparison of results indicated that the proposed 10nm CNTFET based design is more efficient in power savings and speed.


Keywords


CNT, CNTFET, Full Adder Cell, Carry Skip Adder, Design Constraints and Circuit Simulation.



DOI: https://doi.org/10.36039/ciitaas%2F4%2F6%2F2012%2F106913.243-247