Abstract Views :196 |
PDF Views:1
Authors
Affiliations
1 Department of ECE at Dr.M.G.R. University, Chennai, IN
2 ECE Department at Dr.M.G.R. University, Chennai, IN
Source
Artificial Intelligent Systems and Machine Learning, Vol 4, No 3 (2012), Pagination: 141-147
Abstract
A new methodology in partitioning of hardware/software that helps to complete the tasks in time without missing the deadlines is proposed. The scheme is endowed with a sensible and swift hardware elucidation to the quandary of irregularity between data and metadata in multiprocessor systems when information flow tracking functionality is decoupled from the main core. This resolution influences cache lucidity mechanisms to witness interleaving of memory operations from application threads and repeat the same order on metadata processors to preserve uniformity thereby permit approved implementation of dynamic scrutiny on multithreaded programs. Maintains reliability even when a graphics code is moved from user mode to kernel mode. Thus, there is no degradation violation in the proposed scheme. Also, a multistage process approach is used in the present work to allocate and there is no need to alter the applications that are run subsystems are created and allocated dynamically such that any user mode process are offered to run programs across different operating system.
Keywords
H/w/S/w Partitioning, Inter Process Communication, Security, Scheduler.
