Power Efficient Bilateral Filter for Image Denoising

This paper describes the power efficient field programmable gate array implementation of bilateral filter for image denoising. This paper reduces the computational complexity and power dissipation. Reduction of power dissipation is achieved by reducing the unwanted transitions in the adders of bilateral filter. For this purpose, the adder is divided into two parts (Most Significant Part and Least Significant Part).The most significant part is turned off when it does not produce any change in the computation results. Furthermore this paper proposes a highly parallelized bilateral filter structure to reduce the computational complexity.