An Improved High Speed ASIC Hardware Design for Lifting Schemes Using Xilinx Platform Studio

In this paper we propose a technique for software-implementation of an lifting with the goal of getting a customizable lifting DWT-core which can be used as a module in implementing a bigger system irrespective of ones choice of implementation platform. Here we have written the core processor Microblaze is designed in VHDL (VHSIC hardware description language), implemented using XILINX ISE 8.1 Design suite the algorithm is written in system C Language and tested in SPARTAN-3 FPGA kit by interfacing a test circuit with the PC using the RS232 cable. The test results are seen to be satisfactory. The area taken and the speed of the algorithm are also evaluated. It improves throughput 1.35 times greater than the previous design. The Previous design gives throughput upto 93.47MHz.This Proposed System gives the high throughput and it increases the computation speed. For this application it can be used in image processing applications.