A Novel Implementation of Watermarking Techniques for IP Core Identification

In order to reduce the time to market and increase productivity in SOC design, reuse of previously designed modules is becoming a common practice. Design reuse leads to the development of IP identification circuits. This paper presents the identification of the intellectual-property (IP) in SOC (System-On-Chip) design using watermarking algorithm. IP identification procedures depend on current IP-based design flow. A watermark-generating circuit (WGC) and test patterns are embedded into the IP core at the behavior design level. Therefore, this scheme can also successfully survive synthesis, placement, and routing. It can identify the IP at various design levels. Five methods are used to combine WGC and test patterns. Depending upon these methods, the watermark sequence and test patterns are combined and produces the output. From this, identification of the IP can be done. The identity of the IP is proven during the general test process without implementing any extra extraction flow. After the chip has been manufactured and packaged, it is easy to detect the identification of the IP provider. There is no need of microphotograph. This scheme has the advantages of low hardware overhead, low tracking costs, and low processing-time costs.