An Efficient Canonical Signed Digit Multiplier Design for Image Processing Applications

The main objective of today’s circuit design is to increase the performance without the proportional increase in power consumption. In this regard, reversible logic has become a promising technology in the field of low power computing, image processing applications and designing in implementation of Digital Signal Processing (DSP) algorithms in hardware, such as Field Programmable Gated Arrays (FPGAs) that requires a large number of multiplications. The arithmetic operations involved in signal processing systems increases computation complexity which in turn is related to system performance and hardware requirement. There are various methods which help to reduce the computation complexity significantly. In this research work, a reversible Canonical Signed Digit (CSD) multiplier structure is introduced. The various operations like arithmetic and logical operations, address decoding and indexing etc., require data shifting and rotating. For high speed applications the barrel shifters become more popular which can shift and rotatemultiple bits in a single cycle. For this reason, this research work presents an efficient design of a reversible CSD multiplier, which in turn uses the barrel shifter to perform the shifting operation. The main focus is on designing an efficient multiplier and then evaluates several significant parameters for this reversible circuit design. The experimental results shows that the proposed reversible CSD multiplier resulted better in terms of 10% reduced power consumption and 11% increased speed to those generated from the conventional CSD multiplier.