Modified FFT Algorithm and its Application in Digital Image Processing System

Digital Signal Processing (DSP) is used in many application such as image processing, speech processing, video compression, digital set top box, cable modems, digital versatile disk, portable video systems, computers, digital audio, multimedia and wireless communications and digital radio. The field of DSP has always being driven by the advances in DSP applications and scaled Very Large Scale Integration(VLSI) technologies. Therefore, at any given time, DSP applications impose several challenges on the implementations of the DSP systems. It requires complex algorithm to implement those application. This limit the performance of DSP system. These algorithm need to be transformed for design of high speed or low power implementations. One of the essential algorithm for implementing VLSI Digital Signal Processing is Fast Fourier Transform(FFT). It needs n/2log2n multiplication arithmetic nlog2n addition arithmetic. Design of those adders and multipliers uses various implementation styles, such as Ripple Carry Adder (RCA), Carry Skip Adder (CSK), Carry Select Adder and Carry Look ahead Adder (CLA) Error may occurs while implementing those adders. The concept of Error Tolerance (ET) is introduced to improve the performance. To deal with error-tolerant problems, some Truncated adders/multipliers have been reported, but are not able to perform well in either its speed, power, area, or accuracy. Of course, not all digital systems can engage the error-tolerant concept. In digital systems such as control systems, the correctness of the output signal is extremely important, and this denies the use of the error- tolerant circuit. However, for many digital signal processing systems that process signals relating to human senses such as hearing, sight, smell, and touch, e.g., the image processing and speech processing systems, the error-tolerant circuits may be applicable.