Digital Image Processing

C. Kumar Charlie Paul ¹, K. Megala Devi ¹, M. Hemapriya ¹, J. Felcia Jerline ²

Affiliations
1 Indus College of Engineering, IN
2 Dr. G.U. Pope College of Engineering, IN

Abstract

This paper presents a low power vlsi based noise removal and the experiments show, the proposed technique performs significantly better than standard median filter and achieves superior image quality. The intensity of impulse noise has the tendency of being either relatively high or relatively low. Thus, it could severely degrade the image quality and cause great loss of information details. So it is important to eliminate noise in the images before some subsequent processing. Image processing functions, like FIR filtering, pattern recognition or correlation, where the parallel implementation is supported by architecture matched special purpose arithmetic;high throughput FPGA circuits easily outperform even the most advanced DSP processors. Then Adaptive Median Filter solves the dual purpose of removing the impulse noise from the image and reducing distortion in the image. Adaptive Median Filtering can achieve the filtering operation of an image corrupted with impulse noise.

Keywords

FPGA, FIFO.

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C. Kumar Charlie Paul ¹, K. Megala Devi ¹, M. Hemapriya ¹, J. Felcia Jerline ²

Affiliations
1 Indus College of Engineering, IN
2 Dr. G.U. Pope College of Engineering, IN

Abstract

This paper introduces, a new intelligent hardware module suitable for the computation of an adaptive median filter is presented for the first time. The noise detection procedure can be controlled so that a range of pixel values is considered as impulse noise. In this way, the blurring of the image in process is avoided, and the integrity of edge and detail information is preserved. Experimental results with real images demonstrate the improved performance. The proposed digital hardware structure is capable to process gray-scale images of 8-bit resolution and is fully pipelined, whereas parallel processing is used in order to minimize computational time. In the presented design, a 3×3 or 5×5 pixel image neighborhood can be selected for the computation of the filter output. However, the system can be easily expanded to accommodate windows of larger sizes. The proposed digital structure was designed, compiled and simulated using the Modelsim and Synthesized in Xilinx.

Keywords

AMF, FPGA.

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