Design of Wallace Tree Multiplier Using Modified Carry Save Adder

Arithmetic and Logic Unit (ALU), core unit of a processor, when used for scientific computations, will spend more time in multiplications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reducing delay in the multiplier reduces the overall computation time. Wallace multipliers perform in parallel, resulting in high speed. It uses full adders and half adders in their reduction phase. Reduced Complexity Wallace multiplier will have fewer adders than normal Wallace multiplier. A new 16×16 multiplier is proposed with fast adders at the final stage of Wallace multipliers to reduce the delay. The presence of larger carry propagating adder indicates wallace multiplier as faster multiplier. The fast adder (Modified carry save adder) is used at the final stage of the Wallace multipliers to reduce the delay. This paper presents a detailed analysis of several fast adder architectures for high performance VLSI design.