Economic Power Speed Daubechies Wavelet Filter Using VLSI

A novel algebraic integer (AI) based multien- coding of Daubechies-12 2-D wavelet filters having error-free integer-based computation. Digital VLSI architectures empl- oying parallel channels are proposed, physically realized and tested. The multi-encoded AI framework allows a multiplication-free and computationally accurate architect- ture. It also guarantees a noise-free computation throughput the multi-level multi-rate 2-D filtering operation. A single final reconstruction step (FRS) furnishes filtered and down-sampled image outputs in fixed-point, resulting in low levels of quantization noise. Daubechies-12 designs in terms of SNR, PSNR, hardware structure and power consumptions, for different word lengths are compared to Daubechies-12 and -6. SNR and PSNR improvements of approximately 41% were observed in favors of AI-based systems, when compared to 8-bit fixed-point schemes (six fractional bits). Further, FRS designs based on canonical signed digit representation and on expansion factors are proposed. The Daubechies-12 4-level VLSI architectures are prototyped on a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device at 282 MHz and 146 MHz, respectively, with dynamic power consumption of 164 mW and 339 mW, respectively, and verified on FPGA chip using an ML605 platform.