An FSM Based Memory Architecture to Valuate Memory Fault for OFDM

R. Cauvery; B. Muthupandian; R. Ganesan

An FSM Based Memory Architecture to Valuate Memory Fault for OFDM

R. Cauvery ¹, B. Muthupandian ², R. Ganesan ³

Affiliations
1 VLSI Design from Sethu Institute of Technology, Anna University, Chennai, India
2 Department of ECE Design, Sethu Institute of Technology, India
3 Department of M.E-VLSI Design at Sethu Institute of Technology, India

Todays emerging technology is to integrate the electronic device which arises memory fault in system and also occupy more space. Here, proposed that Finite state machine based soft memory repair strategy to reduced access time, lesser occupancy of circuit board and lower power consumption. Linear-Density Parity-Check (LDPC) decoder was used in architecture to provide acceptable error tolerance, and implement of an orthogonal frequency-division multiplexing (OFDM) system as measured by the Bit Error Rate (BER) and the Packet Error Rate (PER). The proposed memory strategy was improved at 0.52 dB gain.