On Chip Fast Cluster Convergence and Reduced Complexity Scheme for Vector Quantizers

Due to advantages of vector quantization (VQ) over scalar quantization, VQ became most favorable scheme for systems where extreme fast decoders are needed. An algorithm using constrained codebook, based on full search VQ and Hierarchical VQ is proposed here. It performs appropriate cluster search depending on the two inequalities defined as positive polarity and negative polarity. This reduces the searching time of the codebook by (N-(NCc×(NC-1))) codevectors. Where N, NC and NCc are total number of reference code vectors, number of clusters and number of code vectors in a cluster respectively. For developed algorithm a processor architecture supporting its computational requirements is also proposed. Processor makes use of pipelining, parallelism, and data control path. The processor performs fast nearest matching codevector search compared to FSVQ by (NCc+NC/N) amount and compared to tree search by (NCc+(NC/log2N)). It also outperforms hierarchical VQ with k-dimensional input and n-bit Nh codevectors codebook as it requires k×Nh search complexity against the complexity of (1×(NCc+NC)) proposed algorithm. The dedicated optimized chip has been designed and laid out using CMOS technology.