Implementation of Test Data Compression for Huffman Decoder

Huge data system applications require storage of large volumes of data set, and the number of such applications is constantly increasing as the use of computers extends to new disciplines. At the same time, the proliferation of communication networks is resulting in massive transfer of data over communication links. Compressing data to be stored or transmitted reduces storage and communication costs. When the amount of data to be transmitted is reduced, the effect is that of increasing the capacity of the communication channel. Here efficient method for decoding the compressed data is proposed. This paper aims toward the implementation of a high speed Huffman decoding system. This proposed model enhances the speed of decoding operation. The model is implemented using VHDL language, simulated on Active HDL 5.1, synthesized, placed and routed and floorplaned using Xilinx tools.