Low Power Synthesis Methodology for Fixed Point FIR Filter Using LCCSE Method

We present a novel finite-impulse response(FIR) filter synthesis technique that allows for aggressive voltage scaling by exploiting the fact that all filter coefficients are not equally important to obtain a ―reasonably accurate‖ filter response .Our technique implements a level constrained common subexpression elimination algorithm, where we can constrain the number of full adder levels(ALs) required to compute each of the coefficient outputs. By specifying a tighter constraint (in terms of the number of adders in the critical path) on the important coefficients, we ensure that the later computational steps compute only the less important coefficient outputs. In case of delay variations due to voltage scaling and/or process variations, only the less important outputs are affected, resulting in graceful degradation of filter quality. The proposed method we are using lccse algorithm, to reduce the adder level and also power and area to compute each of the coefficients output. In proposed work, we are using conditional carry adder to reduce computational complexity of FIR filter and also reduce the power and area. The average power savings of 25%-30%.