Digital Signal Processing

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Circuit-Level Model of Dual-Gate Bi-Layer and Multi-Layer Graphene Fet


Affiliations
1 Department of Information and Communication Engineering, S.K.P Engineering College, Tiruvannamalai-606611, India
2 Information and Communication Engineering, SKP Engineering College, Tiruvannamalai, Tamil Nadu, India
     

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This paper presents Circuit level model of a dual gate bilayer and four layers GFET. This model accurately estimates the conductance at the charge neutrality point (CNP). At the CNP, the device has its maximum resistance, (i) Validates the device off-current for a range of Electric field perpendicular to channel (ii) Estimates the amount of bandgap opening created by application of Electric field using the general Schottky equation. (iii) Validates the channel output conductance against varying gate voltage for both a bilayer and four layer graphene channels.
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  • Circuit-Level Model of Dual-Gate Bi-Layer and Multi-Layer Graphene Fet

Abstract Views: 162  |  PDF Views: 2

Authors

R. Revathi
Department of Information and Communication Engineering, S.K.P Engineering College, Tiruvannamalai-606611, India
Mohan Kumar
Information and Communication Engineering, SKP Engineering College, Tiruvannamalai, Tamil Nadu, India

Abstract


This paper presents Circuit level model of a dual gate bilayer and four layers GFET. This model accurately estimates the conductance at the charge neutrality point (CNP). At the CNP, the device has its maximum resistance, (i) Validates the device off-current for a range of Electric field perpendicular to channel (ii) Estimates the amount of bandgap opening created by application of Electric field using the general Schottky equation. (iii) Validates the channel output conductance against varying gate voltage for both a bilayer and four layer graphene channels.