Digital Signal Processing

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Design and Simulation of Serial and Parallel PG-LDPC Decoder


Affiliations
1 Department of Electronics and Communication, VV College of Engineering, V.V. Nagar, Tisaiyanvilai (Via)-627657, Tirunelveli (Dist.), India
2 Department of Electronics and Communication, Infant Jesus College of Engineering and Technology, Keelavallanadu-628851, India
     

   Subscribe/Renew Journal


This paper aims to develop a serial and parallel Projective geometric LDPC decoder. The Low-Density Parity-Check codes are among the most powerful forward error correcting codes. LDPC codes are recently used for many high bandwidth applications. A parallel decoding scheme is also proposed to shorten the decoding time. Parallel architecture is employed here to increase the throughput. The proposed decoder is verified through simulation and the results are presented. In this work, Xilinx/Modelsim simulations of the serial and parallel Projective geometric LDPC decoder have been performed With the (7,3) PG-LDPC code, the implemented parallel decoder requires less decoding time than the serial decoder.

Keywords

Projective Geometric (PG), LDPC.
User
Subscription Login to verify subscription
Notifications
Font Size

Abstract Views: 193

PDF Views: 2




  • Design and Simulation of Serial and Parallel PG-LDPC Decoder

Abstract Views: 193  |  PDF Views: 2

Authors

M. M. Vijay
Department of Electronics and Communication, VV College of Engineering, V.V. Nagar, Tisaiyanvilai (Via)-627657, Tirunelveli (Dist.), India
K. Mohaneswari
Department of Electronics and Communication, Infant Jesus College of Engineering and Technology, Keelavallanadu-628851, India

Abstract


This paper aims to develop a serial and parallel Projective geometric LDPC decoder. The Low-Density Parity-Check codes are among the most powerful forward error correcting codes. LDPC codes are recently used for many high bandwidth applications. A parallel decoding scheme is also proposed to shorten the decoding time. Parallel architecture is employed here to increase the throughput. The proposed decoder is verified through simulation and the results are presented. In this work, Xilinx/Modelsim simulations of the serial and parallel Projective geometric LDPC decoder have been performed With the (7,3) PG-LDPC code, the implemented parallel decoder requires less decoding time than the serial decoder.

Keywords


Projective Geometric (PG), LDPC.