Digital Signal Processing

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Implementation of 8 Bit Ripple Carry Adder and Serial Adder Using Clocked Adiabatic Logic


Affiliations
1 VIT University, Vellore, Tamilnadu, India
2 School of Electronics, Vellore Institute of Technology, University Vellore, Tamilnadu, India
     

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This paper presents the design of adders using the ultra low power two phase clocked adiabatic logic. Using this logic the basic NAND, NOR, EXOR is designed for designing the 8bit ripple carry adder and the D-flip-flop is constructed using the adiabatic NAND logic and the shift register is evaluated using the D flip-flop to design the serial adder and the performance parameters such as energy dissipation, frequency of operation, are compared with static CMOS and from the results found that it saves up to 70% of power.
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  • Implementation of 8 Bit Ripple Carry Adder and Serial Adder Using Clocked Adiabatic Logic

Abstract Views: 169  |  PDF Views: 1

Authors

N. Vinothkumar
VIT University, Vellore, Tamilnadu, India
V. Vignesh
VIT University, Vellore, Tamilnadu, India
S. Ravi
School of Electronics, Vellore Institute of Technology, University Vellore, Tamilnadu, India

Abstract


This paper presents the design of adders using the ultra low power two phase clocked adiabatic logic. Using this logic the basic NAND, NOR, EXOR is designed for designing the 8bit ripple carry adder and the D-flip-flop is constructed using the adiabatic NAND logic and the shift register is evaluated using the D flip-flop to design the serial adder and the performance parameters such as energy dissipation, frequency of operation, are compared with static CMOS and from the results found that it saves up to 70% of power.