Harmonics Reduction in Multilevel Inverter Systems

The Multilevel inverter is a promising power electronics topology for high-power applications because of its low electromagnetic interference (EMI) and high efficiency with low-switching-frequency control method. The various topologies of Multilevel Inverter (MLI) are diode-clamped, capacitor clamped and cascaded H-bridge inverter. Amongst these topologies, the multilevel cascaded inverter was introduced in static var compensation and drive systems. Traditionally, each phase of a cascaded multilevel inverter requires n dc sources for 2n+1 level. This paper focuses on 5-level cascaded MLI using two unequal dc sources in order to produce a seven-level output. This proposed topology reduces the number of dc sources and switching elements. Various modulation methods have been reported for the MLI, but this paper emphasis on unipolar Inverted Sine PWM (ISPWM) technique. The unipolar Inverted Sine Carrier Pulse-Width Modulation (ISCPWM) technique enhances the fundamental output with reduction in Total Harmonic Distortion (THD), and switching losses. The proposed PWM strategy for three-phase multilevel inverter ensures efficient voltage utilization and gives a better harmonic spectrum and is done using MATLAB. Computer simulation results using MATLAB program are reported and discussed.