Design of Low Power High Performance Parallel-Prefix Adders

The necessity of designing high speed and low power arithmetic circuits suitable for computationally intensive applications has motivated the design of a high performance arithmetic unit using high speed parallel prefix adder architectures. The present work comprises of designing high performance low power adders. Ling and kogge stone adder is designed for power analysis based on parallel prefix adder structure. For the present work, 0.125μm technology has been used. The average power consumed of the both the adders is found at a supply voltage of 5V. From the analysis made Ling adder is found to consume less power than the kogge stone adder. Ling adders designed based on the ling's algorithm. The whole simulation has been done using TSPICE S-Edit.