Netlist to GDS-II Implementation with Effective QoR for Power Optimization and Flow for DSM Technology for ASIC

With semiconductor industry’s aggressive march towards submicron & Deep submicron technology, it is crucial for the IC design to understand the challenges posed by these potential technology changes. Expanding speed and many-sided quality of configuration gives a huge increment in power utilization in VLSI chips. Speed, power utilization and region are real issues in VLSI circuit. To meet these difficulties there are sure outline strategies which are utilized to lessen power. In this Paper I have perform whole Physical Design flow start from Floor Planning done Macro Placement, decide core area and utilization of block. Provide Power structure to block with ensure that each element can get power. Perform Placement of standard cells with power optimization constrain. Provide clock to each and every sequential elements in Clock Tree synthesis stage. Complete Routing stage with four step strategy with provides actual physical metal nets to component. And Optimization of power can be done by considering various components such as transistor sizing, multiple threshold voltages (MTCMOS), Clock gating Technique (use in CTS), Swapping of Cell into High voltage Threshold in non critical Path to Reduce leakage Power.