Power Supply Noise Reduction Circuit for Mixed Signal VLSI Systems

Noise is a significant factor in the analog and digital circuits which determine the characteristics of the system. The speed at which a digital gate switches depends on the clock frequency. A digital system is made up of large a number of digital gates. When the clock frequency is high and several gates switch simultaneously, the surge current will be high. The surge current loads the power supply, causing power supply noise.  The primary cause of power supply noise is the parasitic resistance and inductance associated with power rails of the integrated circuit. The peak current causes considerable voltage drop across the parasitic resistance and inductance, leading to reduction in the power supply available to the system. In most cases the peak power supply noise is the ischolar_main cause of the system failure. So it is inefficient to monitor the signature of transient power supply noise. Methods are proposed to find the peak value of power supply noise using withholding circuits and monitor the corresponding signature. In this work, a power supply stabilization circuit with negative feedback is proposed and utilized for power supply stabilization. The noise voltage is -52.04 dBVrms observed at 100 KHz and it is considerably very less when compared with the existing technique with noise voltage of -24.47 dBVrms. The proposed method can be easily being combined with other existing methods to further reduce the noise.