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Sahu, Anil Kumar
- A Fourth Order 1.8V Power Supply Loop Filter in Continuous Time Delta-Sigma ADC Implemented in 0.18-um CMOS Technology
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Affiliations
1 SSGI, Bhilai, IN
1 SSGI, Bhilai, IN
Source
Digital Signal Processing, Vol 8, No 4 (2016), Pagination: 98-102Abstract
The use of a fourth order loop filter within a Continuous-Time (CT) ΔΣ Analog-to-Digital Converter (ADC) structure is explored and a custom prototype in a 0.18μm CMOS with a measured performance of 40dB gain, 70 degree phase margin and unity gain bandwidth of 79.060 MHz which consuming low power consumption at 1.8V power supply. A key innovation is the explicit use of the loop filter output to avoid the signal distortion that had severely limited the performance of ΔΣ ADC's. The proposed architecture consists of the loop filter using active RC integrators in a low power. This study is implemented in Tanner Tools by using 0.18μm CMOS process.Keywords
Analog to Digital Converter (ADC), Operational Amplifier (OPAMP), Resistor Capacitor (RC) Integrator.
- Hardware Efficient Transceiver Microcell Architecture of USB 2.0 for High Speed Data Communication Using FPGA
Abstract Views :167 |
PDF Views:2
Authors
Affiliations
1 SSTC, Bhilai, IN
1 SSTC, Bhilai, IN
Source
Digital Signal Processing, Vol 7, No 4 (2015), Pagination: 102-105Abstract
In this paper USB 2.0 transceiver architecture using innovative approach presented for high speed data communication. Implemented Universal Serial Bus (USB) Transceiver Macro cell is well suited for high speed data communication and also capable of handling data output relative to input as high as what USB 2.0 demands. Design is implemented on hardware of a Spartan-3FPGA. High-speed to access peripheral interfaces like USB 2.0 is coded in Veriog HDL. Result shown paper hardware efficient and test bench verification is done.Keywords
USB.2.0, Transmitter, Receiver.- Design and Development of Output Response Analyzer for the BIST of Sigma-Delta Modulator
Abstract Views :174 |
PDF Views:2
Authors
Affiliations
1 SSTC, Bhilai, IN
1 SSTC, Bhilai, IN
Source
Digital Signal Processing, Vol 7, No 4 (2015), Pagination: 106-111Abstract
Testing of high resolution second order sigma delta (ΣΔ) modulator is a very expensive process. With the advanced technology, where the complexity over a small area is increasing, then testing at low cost with good accuracy is becoming a tedious issue for the manufacturing process. The cost effectiveness can be calculated on the basis of different parameters of the ΣΔ modulator such as SNDR, ENOB, Gain, Offset, THD, SNR etc. Testing time also play an important role in the cost effectiveness of the modulator. The Built-in-self-test (BIST) allows the machine or circuit to test itself. BIST is desirable for the VLSI system in order to reduce the cost per chip of production-time testing by the manufacture, it can also provide the means to perform in-the field diagnostic. Therefore, this paper will demonstrate a possibility to simplify modeling and simulation of testing strategy of high-resolution ΣΔ modulator using MATLAB SIMULINK environment. Here, we are finding the cost effectiveness on the basis of Signal to Noise Distortion Ratio (SNDR) for the ΣΔ modulator BIST. A ΣΔ modulation based signal generator is considered which can produce analog sinusoidal test stimuli and digital reference signal on chip. By comparing the ADC output with that of the generator reference signal, the parameter can be determined on chip based on the standard equations in the proposed simulation environment.Keywords
Sigma-Delta Modulator (ΣΔ), Signal-To-Noise Ratio (SNR), Output Response Analyzer (ORA), Integrated Nonlinearity Error (INL), Built-In-Self Test (BIST), Dynamic Nonlinearity Error (DNL).- Low Noise Elliptical Filter in 250 Nanometer Technology for EEG Signals
Abstract Views :160 |
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Digital Signal Processing, Vol 8, No 5 (2016), Pagination: 126-129Abstract
A low noise filter for low frequency is presented. 5th order elliptical Filter design using OTA-C method is low in noise and good to acquire biopotential signal in range of 40 Hz. Filter provides strong attenuation against power line interference which occurs due to power supply of a system. For achieving low noise and low transconductance, current division and current cancellation technique (CDCC) is applied.
Filters also have a total harmonic distortion of 1.6 % with 50 millivolt peak to peak signals. OTA used CDCC topology provide the low transconductance required for low frequency application. OTA work in sub threshold region with bias current of 300 Nano amperes and also have a tuning ability with vtune voltage and it is biased with simple current mirror. This entire circuit design in 250 nanometer technology with 2.5 volt power supply using T-SPICE simulator of tanner EDA 15. Bandwidth and noise of a filter is 38 Hz, 3.36µvolt/ respectively.