Digital Signal Processing

A. N. Jayanthi ¹, C. S. Ravichandran ²

Affiliations
1 Department of ECE, Sri Ramakrishna Inst of Technology, Coimbatore, IN
2 Sri Ramakrishna Engineering College, Coimbatore, IN

Abstract

The Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope of reducing the area consumption in the CSLA. This work uses a simple and efficient gate-level modification technique to reduce the area of the CSLA. Based on this modification 8-, 16-, 32-, 64- and 128-b square-ischolar_main CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area as compared to the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area and their products by hand with logical effort and through custom design and layout in 0.18-um CMOS process technology. The result analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Keywords

CSLA, ASIC, CSA, BEC.

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A. N. Jayanthi ¹, C. S. Ravichandran ²

Affiliations
1 Department of ECE, Sri Ramakrishna Institute of Technology, Coimbatore-10, IN
2 SSK College of Engineering and Technology, Coimbatore, IN

Abstract

Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to high energy consumption. To reduce the energy consumption of the LDPC decoder, memory-bypassing scheme has been proposed for the layered decoding architecture which reduces the amount of access to the memory storing the soft posterior reliability values. In this work, a scheme that achieves the optimal reduction of memory access for the memory bypassing scheme is presented. The amount of achievable memory bypassing depends on the decoding order of the layers. In this proposal the problem of finding the optimal decoding order and propose algorithm to obtain the optimal solution and also the corresponding architecture which combines some of memory components and results in reduction of memory area.

Keywords

Low Power, Low-Density Parity-Check Code, Simulated Annealing.

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