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Authors
Affiliations
1 Electronics and Communication Department, SRM University, Chennai, IN
Source
Digital Signal Processing, Vol 3, No 7 (2011), Pagination: 318-323
Abstract
This research work presents an efficient implementation of Finite Impulse Response Filter (FIR) using Distributed Arithmetic (DA) architecture. Here, the multipliers in FIR filter are replaced with multiplier less DA based technique. The DA based technique consists of Look Up Table (LUT), shift registers and scaling accumulator. Analysis on the performance of various orders of the digital FIR filter with various methods of sections on different address length of partial tables are done using Xilinx 12.3 synthesis tool. The proposed architecture provides an efficient Very Large Scale Integration (VLSI) implementation which involves significantly less latency and less area-delay complexity when compared with existing structures of the digital FIR Filter. In this method, the multiplier less FIR filter is implemented using Distributed Arithmetic which consists of Look Up Table and then its partitioning is involved. This technique reduces the delay by 15%, area by 34% and LUT by 75%.
Keywords
Distributed Arithmetic (DA), Finite Impulse Response (FIR), Field Programmable Gate Array (FPGA), Look up Table (LUT).
