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Nagarajan, G.
- Power Supply Noise Reduction in Mixed Signal System-On-Chip with Active Decoupling Inductor
Authors
1 Department of ECE, Pondicherry Engineering College, Pondicherry, IN
2 Department of ECE, Pondicherry Engineering College, Pondicherry, IN
Source
Digital Signal Processing, Vol 9, No 2 (2017), Pagination: 17-25Abstract
When integrating analog and digital circuits onto a mixed-mode chip, power supply noise is a major limitation on the performance of the analog circuitry. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates. This paper introduces an active inductor implementation and analyze the various characteristics of the active inductor in the practical scenario. The proposed CMOS active inductor exhibits better power supply noise rejection of 30 dB when the inverter circuit is used as the load. The proposed CMOS active inductor circuit is implemented in GPDK 180nm CMOS technology. Also the simulation result shows that the noise measured is only 5.788 μV with active inductor whereas the noise measured without active inductor is 50 mV.
Keywords
CMOS Active Inductor, Deep Sub-Micron, Power Supply Noise, Technology Scaling.
- Harmonizing Mechanism for Power Saving and Delay Reduction in LTE Networks using DRX
Authors
1 Department of ECE, SCSVMV University, IN
2 Department of ECE, Pondicherry Engineering College, IN
Source
Digital Signal Processing, Vol 9, No 2 (2017), Pagination: 31-34Abstract
The need of User Equipment (UE) has been increasing day by day. This has henceforth necessitated the need for the investigation of the power consumed in the user equipment during switching process and to come up with a method to reduce the power loss that occurs in the system. This is achieved using Discontinuous Reception Mechanism (DRX).DRX is a methodology proposed in Long Term evolution-LTE networks to achieve more power saving. DRX mechanism also has the tendency to introduce latency in the system. Using the DRX mechanism the power that can be saved in active and background traffic is comparatively good. This paper focuses on optimizing power saving in UE and to reduce latency introduced in the process. By properly scheduling the DRX parameters, an optimized output with proper power saving and less latency can be obtained. Results show that, a better quality and lifetime of user equipment can be obtained.