Digital Signal Processing

P. Rajeswari ¹, G. Venkata Subramanian ², N. Suresh Kumar ³, S. Raju ⁴

Affiliations
1 Department of ECE, Velammal College of Engineering and Technology, IN
2 Department of ECE, Mepco Schlenk Engineering College, IN
3 Velammal College of Engineering and Technology, IN
4 Department of ECE, Thiagarajar College of Engineering, IN

Abstract

The role of interconnects in integrated circuit performances has considerably increased with the technology scale down. Hence interconnect signal integrity becomes much more important, due to the smaller feature sizes and wire pitches. Devices with faster rise and fall times (typically tens of picoseconds) make global interconnects such as clock nets, bus signals, power/ground grids, more vulnerable to signal integrity (SI) degradations. Meanwhile, nanometer process technologies have increased manufacturing and lithography-based distortions of wires, dielectrics, and devices. Starting with the 130nm generation, the interconnect delay began to surpass the intrinsic gate delay. Since most of the delay comes from the IC's interconnect, the tool flow needs accurate interconnect delay information as early as possible and should allow continuous optimization in different stages to correctly reflect the real interconnect delay. The power consumption, performance, signals and power integrity are all affected by the chip interconnect. In addition, minimizing the signal integrity effects such as crosstalk, reflections loss, attenuation, insertion loss, etc., is also a major challenge in the nanometer design. Hence the signal integrity analysis of high-speed electronic designs at nanometer range requires a specific design methodology. In this paper, a single pass SI-aware design methodology is adopted; whose design flow involves three steps. First, the parameters (such as scattering, RLC, Transmission line and near field distributions), which characterize the transmission line structures as interconnect are extracted. Then the frequency range over which the different interconnect structures having minimum losses are found based on the extracted parameters. Next, the nanometer structure selected based on a standard design criterion, is analyzed for various signal integrity effects. Finally, suitable mitigation techniques are adopted so as to eliminate the SI effects.

Keywords

Signal Integrity, Transmission Line Structures, SI Effects, Parameter Extraction.

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