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Authors
Affiliations
1 Department of Information and Communication Engineering, S.K.P Engineering College, Tiruvannamalai-606611, IN
2 Information and Communication Engineering, SKP Engineering College, Tiruvannamalai, Tamil Nadu, IN
Source
Digital Signal Processing, Vol 7, No 3 (2015), Pagination: 68-72
Abstract
This paper presents Circuit level model of a dual gate bilayer and four layers GFET. This model accurately estimates the conductance at the charge neutrality point (CNP). At the CNP, the device has its maximum resistance, (i) Validates the device off-current for a range of Electric field perpendicular to channel (ii) Estimates the amount of bandgap opening created by application of Electric field using the general Schottky equation. (iii) Validates the channel output conductance against varying gate voltage for both a bilayer and four layer graphene channels.
