Digital Signal Processing

V. M. Thoulath Begam ¹, S. Baul Kani ²

Affiliations
1 Electronics and Communication Department, National College of Engineering, Maruthakulam, Tamilnadu, IN
2 Electronics and Communication Department, Government College of Engineering, Tirunelveli, Tamilnadu, IN

Abstract

This paper introduces a novel technique for automatic test pattern generation which well detects both easy to detect faults and hard to detect faults. It also allows to choose the test test pattern which has lower no. of transition to reduce the power dissipation during testing. ATPG based on this SAT technique dynamic clause activation (DCA) generates a limited number of test patterns which can cover more faults. ATPG based on implication graph have problems to cope with hard-to-detect faults. ATPG based on Boolean satisfiability does not work on a structural form. In SAT solver method the problem is transferred in to a Boolean formula and a SAT solver is used to solve this problem. It has disadvantages such as overhead for CNF transformation and over specified solutions. In the proposed method, the solving problem is directed by structural information which is provided dedicated data structures. The technique is designed such that the efficient solving techniques and data structures of SAT solver do not have to be modified. This is a crucial to retain the high efficiency of a SAT based algorithm. The proposed method is fast and provides a very high fault efficiency and useful in large industrial circuit.

Keywords

ATPG, Boolean Satisfiability, CNF, Dynamic Clause Activation, Dynamic SAT, Fault Coverage, SAT.

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