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Seenuvasamurthi, S.
- Power Supply Noise Reduction in Mixed Signal System-On-Chip with Active Decoupling Inductor
Authors
1 Department of ECE, Pondicherry Engineering College, Pondicherry, IN
2 Department of ECE, Pondicherry Engineering College, Pondicherry, IN
Source
Digital Signal Processing, Vol 9, No 2 (2017), Pagination: 17-25Abstract
When integrating analog and digital circuits onto a mixed-mode chip, power supply noise is a major limitation on the performance of the analog circuitry. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates. This paper introduces an active inductor implementation and analyze the various characteristics of the active inductor in the practical scenario. The proposed CMOS active inductor exhibits better power supply noise rejection of 30 dB when the inverter circuit is used as the load. The proposed CMOS active inductor circuit is implemented in GPDK 180nm CMOS technology. Also the simulation result shows that the noise measured is only 5.788 μV with active inductor whereas the noise measured without active inductor is 50 mV.
Keywords
CMOS Active Inductor, Deep Sub-Micron, Power Supply Noise, Technology Scaling.
- Power Supply Noise Reduction Circuit for Mixed Signal VLSI Systems
Authors
1 Department of ECE, Pondicherry Engineering College, Pondicherry, IN
2 Department of ECE, Pondicherry Engineering College, Pondicherry, IN
Source
Digital Signal Processing, Vol 9, No 2 (2017), Pagination: 26-30Abstract
Noise is a significant factor in the analog and digital circuits which determine the characteristics of the system. The speed at which a digital gate switches depends on the clock frequency. A digital system is made up of large a number of digital gates. When the clock frequency is high and several gates switch simultaneously, the surge current will be high. The surge current loads the power supply, causing power supply noise. The primary cause of power supply noise is the parasitic resistance and inductance associated with power rails of the integrated circuit. The peak current causes considerable voltage drop across the parasitic resistance and inductance, leading to reduction in the power supply available to the system. In most cases the peak power supply noise is the ischolar_main cause of the system failure. So it is inefficient to monitor the signature of transient power supply noise. Methods are proposed to find the peak value of power supply noise using withholding circuits and monitor the corresponding signature. In this work, a power supply stabilization circuit with negative feedback is proposed and utilized for power supply stabilization. The noise voltage is -52.04 dBVrms observed at 100 KHz and it is considerably very less when compared with the existing technique with noise voltage of -24.47 dBVrms. The proposed method can be easily being combined with other existing methods to further reduce the noise.