Digital Signal Processing

P. Tirumala Rao ¹, P. Siva Kumar ¹, Y. V. Apparao ², N. Santosh Kumar ¹

Affiliations
1 ECE Department, Vignan's Institute of Information Technology, IN
2 ECE Department, GITAM University, IN

Abstract

Pulse compression technique is most widely used in radar and communication areas. The radar pulse compression codes must have good merit factor and discrimination factor. But there are several signal design problems which are reported in the literature and these signal design problems can be solved through binary, Ternary, Quinquenary and six phase pulse compression sequences. Hence VLSI architectures to generate such radar pulse compression sequences were developed. But when we are moving from binary to ternary and ternary to six phase pulse compression VLSI systems, the memory requirements are increased there by the area is increased. The good VLSI design needs optimization of the area, speed, power consumption. This paper concentrates on developing area optimized VLSI architecture to generate radar pulse compression sequences without sacrificing the speed of the system. The other interesting thing about this paper is the proposed single chip VLSI architecture can generate all the phase coded pulse compression sequences like Binary, Ternary, Quaternary, Quinquenary, 6-phase and other poly phase sequences. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability.

Keywords

FPGA, Merit Factor, PULSE Compression, Side Lobe Energy, Six Phase Pulse Compression.

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