Fuzzy Systems

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

A Low Power VLSI Architecture Design Using Enhanced ADPLL


Affiliations
1 Department of ECE, K.S.R College of Engineering, Tiruchengode, Tamilnadu, India
2 Department ECE, K.S.R College of Engineering, Tiruchengode, Tamilnadu, India
3 Department of ECE, K. S. R College of Engineering, Tiruchengode, Tamilnadu, India
     

   Subscribe/Renew Journal


This paper describes the design and implementation of an ADPLL by using Fuzzy logic. The digital phase detector, digital filter loops and digital-controlled oscillators are gradually analyzed. The ADPLL is built entirely from logic circuits and has replaced the classical DPLL in many applications, especially digital communications. The project is to reduce the power and improve the tuning range of frequency. To reduce power the System on Chip is used. The proposed ADPLL is designed using Tanner EDA Tool.

Keywords

All Digital Phase Locked Loop (ADPLL), Phase Frequency Detector (PFD), Time-to-Digital Converter (TDC), Frequency Divider, Digitally Controlled Oscillator (DCO), Programmable Divider, Fuzzy Inference Symbol.
User
Subscription Login to verify subscription
Notifications
Font Size

Abstract Views: 323

PDF Views: 2




  • A Low Power VLSI Architecture Design Using Enhanced ADPLL

Abstract Views: 323  |  PDF Views: 2

Authors

T. M. Sathish Kumar
Department of ECE, K.S.R College of Engineering, Tiruchengode, Tamilnadu, India
P. S. Periasamy
Department ECE, K.S.R College of Engineering, Tiruchengode, Tamilnadu, India
C. Divya
Department of ECE, K. S. R College of Engineering, Tiruchengode, Tamilnadu, India

Abstract


This paper describes the design and implementation of an ADPLL by using Fuzzy logic. The digital phase detector, digital filter loops and digital-controlled oscillators are gradually analyzed. The ADPLL is built entirely from logic circuits and has replaced the classical DPLL in many applications, especially digital communications. The project is to reduce the power and improve the tuning range of frequency. To reduce power the System on Chip is used. The proposed ADPLL is designed using Tanner EDA Tool.

Keywords


All Digital Phase Locked Loop (ADPLL), Phase Frequency Detector (PFD), Time-to-Digital Converter (TDC), Frequency Divider, Digitally Controlled Oscillator (DCO), Programmable Divider, Fuzzy Inference Symbol.