Refine your search
Collections
Co-Authors
Journals
Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Sahu, Anil Kumar
- Modeling of Test Stimulus Generator and CORDIC Logic for Testing of CT Sigma Delta Analog-To-Digital Converter
Abstract Views :172 |
PDF Views:5
Authors
Affiliations
1 Department of ETC, Shri Shankaracharaya Technical Campus (SSTC), Bhilai, IN
2 Department of EEE, Chhatrapati Shivaji Institute of Technology, Durg, IN
3 International Institute of Information Technology (IIIT), Bangalore, IN
1 Department of ETC, Shri Shankaracharaya Technical Campus (SSTC), Bhilai, IN
2 Department of EEE, Chhatrapati Shivaji Institute of Technology, Durg, IN
3 International Institute of Information Technology (IIIT), Bangalore, IN
Source
Fuzzy Systems, Vol 10, No 4 (2018), Pagination: 99-102Abstract
This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK tool environment. Stimuli are applied into the design under test and extract the important static and transmission parameters by means of the response analyzer. There are so many types of stimulus which have different types of properties. Therefore, the test stimuli generator is a key building block in BIST methodology and must be high quality, flexible and easy to realize.Output Response Analyzer (ORA) is most important component in Built-In-Self-Test (BIST) architecture of CT sigma delta ADC. There are many techniques of ORA used for determining performance matrix parameter such as integral non-linearity, differential non-linearity and Signal-to-Noise Ratio (SNR).In this paper suggests CORDIC technique as ORA and it’s modelling and simulation has been implemented on MATLAB simulink tool environment. The COrdinate Rotation Digital Computer (CORDIC) logic is used to reduces the design complexity of circuit.
Keywords
CT Sigma-Delta ADC Structrure, Test Stimuli Generator, Cordinate Rotation Digital Computer (CORDIC) Logic for ORA, Built-In-Self-Test for CT ADC.
References
- Abbes, K., A. Hentati, and M. Masmoudi. "Test and characterization of 1 bit Σ—Δ modulator." In Systems, Signals and Devices, 2008. IEEE SSD 2008. 5th International Multi-Conference on, pp. 1-4. IEEE, 2008.
- Lee, Kuen-Jong, Soon-Jyh Chang, and Ruei-Shiuan Tzeng. "A sigma-delta modulation based BIST scheme for A/D converters." In Test Symposium, 2003. ATS 2003. 12th Asian, pp. 124-127. IEEE, 2003.
- Chouba, Nabil, and Laroussi Bouzaida. "A BIST architecture for sigma delta ADC testing based on embedded NOEB self-test and CORDIC algorithm." InDesign and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on, pp. 1-7. IEEE, 2010.
- Damarla, Raju T., Wei Su, Moon J. Chung, Charles E. Stroud, and Gerald T. Michael. "A built-in self test scheme for VLSI." In Design Automation Conference, 1995. Proceedings of the ASP-DAC'95/CHDL'95/VLSI'95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal, pp. 217-222. IEEE, 1995.
- Hawrysh, Evan M., and Gordon W. Roberts. "An integration of memory-based analog signal generation into current DFT architectures." In Test Conference, 1996. Proceedings., International, pp. 528-537. IEEE, 1996.
- Huang, Jiun-Lang, Chee-Kian Ong, and Kwang-Ting Cheng. "A BIST scheme for on-chip ADC and DAC testing." In Proceedings of the conference on Design, automation and test in Europe, pp. 216-220. ACM, 2000.
- Xing, Hanqing, Hanjun Jiang, Degang Chen, and Randall L. Geiger. "High-resolution ADC linearity testing using a fully digital-compatible BIST strategy." Instrumentation and Measurement, IEEE Transactions on 58, no. 8 (2009): 2697-2705.
- Duan, Jingbo, Degang Chen, and Randall Geiger. "Cost effective signal generators for ADC BIST." In Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp. 13-16. IEEE, 2009.
- Huang, Jiun-Lang, and Kwang-Ting Cheng. "Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis." In Test Conference, 2000. Proceedings. International, pp. 1021-1030. IEEE, 2000.
- Wen, Yun-Che, and Kuen-Jong Lee. "An on chip ADC test structure." In Proceedings of the conference on Design, automation and test in Europe, pp. 221-225. ACM, 2000..
- Bandopadyay, T. K., Manish Saxena, and Raghav Shrivastava. "Sigma Delta Modulator with Improved Performance through Evolutionary Algorithm." International Journal of Science and Research (IJSR) Volume 2 Issue 3, March 2013.
- Benabes, Philippe. "Accurate time-domain simulation of continuous-time sigma–delta modulators." Circuits and Systems I: Regular Papers, IEEE Transactions on 56.10 (2009): 2248-2258.
- C. H. E. N. Zhicai, Mathew Bond, and Nijad Anabtawi. "Design of a Second Order Continuous Time Sigma Delta Modulator with Improved Dynamic Range." Final Project of Oversampling Class, Fall 2007 Arizona State University.
- Hart, Adam, and Sorin P. Voinigescu. "A 1 GHz Bandwidth Low-Pass ADC With 20–50 GHz Adjustable Sampling Rate." Solid-State Circuits, IEEE Journal of 44.5 (2009).
- Toner, Michael F., and Gordon W. Roberts. "A BIST Scheme for an SNR Test of a Sigma-Delta ADC." Test Conference, 1993. Proceedings., International. IEEE, 1993.
- Rolindez, Luis, "A SNDR BIST for/spl Sigma//spl Delta/analogue-to-digital converters." VLSI Test Symposium, 2006. Proceedings. 24th IEEE. IEEE, 2006.
- Prateek Verma, Anil Kumar Sahu ,Dr. Vivek Kumar Chandra, Dr. G.R.Sinha. A Graphical User Interface Implementation of Second Order Sigma-Delta Analog to Digital Converter with Improved Performance Parameters, International Journal For Research In Applied Science And Engineering Technology ,Vol. 2 Issue VII, July 2014.
- Sahu, Anil Kumar, Vivek Kumar Chandra, and G. R. Sinha. "System Level Behavioral Modeling of CORDIC Based ORA of Built-in-Self-Test for Sigma-Delta Analog-to-Digital Converter." International Journal of Signal and Image Processing Issues 2015, no. 2 (2016).
- Sahu, Anil Kumar, Chandra, Vivek Kumar, et. Sinha, G. R. “A Review on System Level Behavioral Modeling and Post Simulation of Builtin-Self-Test of Sigma-Delta Modulator Analog-to-Digital Converter”International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3 no. 2, pp. 206-209.
- Sahu, Anil Kumar, Chandra, Vivek Kumar, et SINHA, G. R. “Improved SNR and ENOB of SigmaDelta Modulator for Post Simulation and High Level Modeling of Built-in-Self Test Scheme.” 2015 International Journal of Computer Applications (0975 – 8887) Applications of Computers and Electronics for the Welfare of Rural Masses (ACEWRM) 2015, pp. 11-14.