Design of 64x64 Bit Parity Preserving Reversible Vedic Multiplier Using Carry Look Ahead Adder

Multiplier play an important role in most of signal processing operations, processors and nanotechnology, quantum computing .The performance of the multiplier is depend upon architecture and the algorithm used for the multiplication operations .The Carry Look ahead Adder is implemented using fault tolerant gate, employed for the partial product addition which is constructed using New fault tolerant Gate (NFT) and Double Feynman gate (F2G). A 64x64 bit fault tolerant and high speed multiplier architecture is proposed. The newly proposed multiplier architecture is based on Urdhva Tiryakbhayam formula from an ancient Indian Vedic Mathematics which produce all partial product and theirs addition in one step and Parity Preserving reversible gate which performs a reversible computation which ensures zero internal power dissipation in a manner that they also detect a fault in the circuit. A newly proposed multiplier have its application in the field of quantum computing, processors, nanotechnology, and Digital Signal Processing. The design of high speed parity preserving reversible vedic multiplier architecture is done in Verilog language and simulated using Xilinx14.7.