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FPGA Implementation of Multi Layer Perceptron Neural Network for Signal Processing


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1 Srinivasan Engineering College, Perambalur, Tamilnadu, India
     

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Artificial Neural Networks support their processing capabilities in a parallel architecture. It is widely used in pattern recognition, system identification and control problems. Multilayer Perceptron is an artificial neural network with one or more hidden layers. This paper presents the digital implementation of multi layer perceptron neuron network using FPGA (Field Programmable Gate Array) for pattern recognition. If the pattern matches with the original then process continued else it is rejected. This network was implemented by using three types of non linear activation function: hardlims, satlins and tansig. A neural network was implemented by using VHDL hardware description Language codes and XC3S250E-PQ 208 Xilinx FPGA device. The results obtained with Xilinx Foundation 9.2i software are presented. The results are analyzed by using device utilization and time delay.

Keywords

FPGA, Multi Layer Perceptron, Neuron Plan Approximation, Sigmoid Activation.
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  • FPGA Implementation of Multi Layer Perceptron Neural Network for Signal Processing

Abstract Views: 224  |  PDF Views: 2

Authors

A. Thilagavathy
Srinivasan Engineering College, Perambalur, Tamilnadu, India
K. Vijaya Kanth
Srinivasan Engineering College, Perambalur, Tamilnadu, India

Abstract


Artificial Neural Networks support their processing capabilities in a parallel architecture. It is widely used in pattern recognition, system identification and control problems. Multilayer Perceptron is an artificial neural network with one or more hidden layers. This paper presents the digital implementation of multi layer perceptron neuron network using FPGA (Field Programmable Gate Array) for pattern recognition. If the pattern matches with the original then process continued else it is rejected. This network was implemented by using three types of non linear activation function: hardlims, satlins and tansig. A neural network was implemented by using VHDL hardware description Language codes and XC3S250E-PQ 208 Xilinx FPGA device. The results obtained with Xilinx Foundation 9.2i software are presented. The results are analyzed by using device utilization and time delay.

Keywords


FPGA, Multi Layer Perceptron, Neuron Plan Approximation, Sigmoid Activation.