An Area Efficient Hard Decision Viterbi Decoder for Software Defined Radio Receiver

Viterbi decoder is working in wireless communications to decode the convolutional codes; those codes are used in every robust digital communication system. Such decoders are complex and waste large amount of power. In software defined radio receiver, field programmable gate array is considered as a highly configure option for software defined radio receiver is described using verilog code in Xilinx software. In this paper, used modification viterbi decoder for this reason reduced power and reduces number of slices, ACS, flip flops that can be implemented on FPGA. In this paper, a low power, adaptive viterbi decoder for SDR receiver is described using a verilog code and used constraint length is 9. The proposed design is implemented on Xilinx Spartan 3e.