Realisation of Pulse Shaping FIR Interpolation Filter Using Digital up Converter

This Optimization technique for designing a configurable VLSI architecture of an interpolation filter for multi-standard digital up converter .RRC filter is used to reduce the area, delay and power consumption. The low current range and architecture of the pulse-shaping FIR filter for digital up converter was developed. In the existing system, the 3bit binary common subexpression(BCS) based (BCSE) elimination algorithm. In this paper carry adder is used instead of the shift and add method and the simple arithmetic adder multiplexer unit is replaced by the carry-save adder. The number of additions and multiplications can be reduced using this technique. This technique has been in reducing the area and power consumption by 25% and 10%, respectively, reported with 68% improvement in operating frequency over a 2-bit BCSE-based technology, and can be considered adequate for designing more the multi-standard DUC. The designed pulse shaping FIR filter synthesized and simulated using Xilinx ISE 6.9.