A Review on Various Hardware Architectures of AES Algorithm

In recent days, the importance of security in the information technology has increased significantly. Advance Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is a cryptographic algorithm that can be used to protect electronic data. With the increasing demand for secure transaction in banking and other such system, encryption and decryption using cryptography algorithm which play a very important role. Nowadays, Most secure transactions occurring on smart phones, commercial uses and other hand-held devices, a low on chip area and a high speed algorithm to perform the same become the need for recent days. In order to achieve higher performance in today's heavily loaded communication networks, hardware implementation is a wide choice in terms of better speed and reliability. In This Review paper present the various hardware Architecture of Advance Encryption standard (AES) algorithm using Xilinx Vertex XCV1000BG560-4 Field Programmable Gate Array (FPGA).