A Novel VLSI Architecture for FIR Filter Using Urdhwa Multiplier Compressor

High performance digital adder with less power consumption and reduced area is a fundamental design issues for advanced processors. Speed and area are now a days one of the important design issues in digital circuits. One of the fastest adder is Carry Select Adder (CSA) which is used in many processors to perform fast arithmetic function. To increase the efficiency of the adder many different adder architecture designs have been developed. As we know per second millions of operations are performed in microprocessors. So while designing of multipliers, speed of operation is one of most important criteria to be considered. Due to which faster multiplier and high speed architecture of adder plays an vital role in many applications. We, in this paper, proposed a technique for designing of FIR filter using urdhwa multiplier compressor and modified carry select adder. Verification of CSA structure is performed and implemented for 16, 32 and 64 bit filter circuits. Comparing with previous existing structure of adder and our proposed design improves the efficiency of adder. These designs are implemented on Xilinx software.