Review Paper on Techniques for Reducing Jitter in PLL

Utsav H. Bhatt; Ekata Mehul; Anurag P. Lakhlani; Amit  Kumar

Review Paper on Techniques for Reducing Jitter in PLL

Utsav H. Bhatt , Ekata Mehul , Anurag P. Lakhlani , Amit  Kumar

Affiliations
1 Department of Electronics and Communication, MEF Group of Institutions, Rajkot-360003, India

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The paper present various possible jitter reduction technique while designing a Phase Locked Loop. Basic block which makes Phase Locked Loop are Phase detector, Loop Filter and Voltage Control Oscillator including suitable feedback. While reducing the jitter of PLL at the output, reduction in bandwidth of loop filter reducing the gain of phase detector, reducing the gain of the VCO, modifying basic building block and several other technique is proposed.