Design a Low Jitter Charge Pump Phase Locked Loop

The paper presents a designing a low jitter Phase Locked Loop (PLL). To reduce the jitter design is modified such that it gives minimal phase variation at the output of voltage controlled oscillator. The design uses phase frequency detector with charge pump configuration. The current source output of charge pump given to the current starved voltage controlled oscillator. The VCO is design of 100 Mhz with 50 nm technology BSIM4 model used for simulation in LTSpice. The design has advantage in lower area as well as faster acquisition time of PLL.