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A High Speed VLSI Architecture for Computation of 2D-Discrete Wavelet Transform


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1 VNRVJIET, India
     

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This paper proposes a method for the design of a high speed VLSI architecture for the computation of 2D discrete wavelet transform on a 256 256 image. To achieve the goal of high speed, the computational task of multi decomposition levels are optimally mapped to the stages of the pipeline and synchronized. The 2-D filtering operation is divided into four subtasks which are performed independently in parallel. To validate the proposed scheme, a circuit is simulated and implemented using Verilog HDL in Xilinx ISE 10.1 on Spartan-3E FPGA board.


Keywords

DWT, Pipeline Architecture, Non-Separable Approach, Multi Resolution Filtering.
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  • A High Speed VLSI Architecture for Computation of 2D-Discrete Wavelet Transform

Abstract Views: 288  |  PDF Views: 1

Authors

Zeba Zareen
VNRVJIET, India
K. Aruna Kumari
VNRVJIET, India

Abstract


This paper proposes a method for the design of a high speed VLSI architecture for the computation of 2D discrete wavelet transform on a 256 256 image. To achieve the goal of high speed, the computational task of multi decomposition levels are optimally mapped to the stages of the pipeline and synchronized. The 2-D filtering operation is divided into four subtasks which are performed independently in parallel. To validate the proposed scheme, a circuit is simulated and implemented using Verilog HDL in Xilinx ISE 10.1 on Spartan-3E FPGA board.


Keywords


DWT, Pipeline Architecture, Non-Separable Approach, Multi Resolution Filtering.