Low Power Test Patterns Generation in BIST Schemes

BIST is a viable approach to test today's digital systems. During self-test, the switching activity of the Circuit Under Test (CUT) is significantly increased compared to normal operation and leads to an increased power consumption which often exceeds specified limits. The proposed method generates Multiple Single Input Change (MSIC) vectors in a pattern. The each generated vectors are applied to a scan chain is an SIC vector. A class of minimum transition sequences is generated by the use of a reconfigurable Johnson counter and a scalable SIC counter. The proposed TPG method is flexible to both the test-per-scan schemes and the test-per-clock. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. As the switching activity is reduced, the power consumption of the circuit will also be reduced.