Analysis of Parameters of 8 Bit Multiplies on Behalf of Power Consumption and Delay

Adders and Multipliers are key components of many high performance systems such as finite impulse response (FIR) filters, microprocessors, digital signal processors, etc. Digital multiplication is one of the most basic functions in a wide range of algorithm. Being the slowest element in the system, the performance of the system is determined by the performance of the multiplier block. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, the primary consideration in multipliers has been and continues to be delay as well as power consumption. Power consumption of the multiplier circuit is a very important issue as this power will add up to the total power consumption of the circuit. Depending upon the application there are different types of multipliers are available. Digital multiplier is fast, reliable and efficient components that are utilized to implement any operation. The multiplier is the prime requirement for now days, by implementation of various components and techniques we can improve the performance of the system. In this paper we optimize the parameters of three different techniques e.g. conventional static CMOS logic, Complimentary pass transistor logic, double pass transistor logic. The parameters are evaluated through TARNER 13 software which is the implementation of Very large Scale Integration for the techniques as discussed in the section.