Hardware Implementation of Digital Filters For Image De-Noising Applications

Suppression or removal of noise from the original image is a challenge. Most of the techniques are already proposed and used in practice. To implement such techniques in any application is important part of the application. Hardware implementations of such techniques become mandatory in today‘s technical aspect of system on chip. In this paper the implementation of content based mean, median filter and wavelet transform suitable for impulse noise suppression is presented. The adaptive median filter detects the existence of impulse noise in an image neighborhood and, the blurring of the image in process is avoided. The integrity of edge and detail information is preserved. The hardware simulation has been carried out using ‗MODELSIM‘ software tool and further implemented in FPGA. For handy and fast industrial imaging applications, this approach is important. A variant of the Haar wavelet transform that uses only addition and subtraction operations is also implemented. A selection strategy, which does not require the previous ordering of coefficients, has been used. The whole compression circuitry has been described and simulated at HDL level for up to 4 consecutive images, obtaining consistent results. The PSNR value of Haar transform is 20%. The complete processor (excluding memory) for images of 256 × 256 pixels has been implemented using only one cheap FPGA chip, thus making the design reliable and relatively simple.