Particle Swarm Optimization Approach for MST Problem in VLSI Routing

The performance of very large scale integration (VLSI) circuits predominantly depends on routing of interconnected circuits. The major problems in the design of VLSI layouts are wire sizing, buffer sizing and buffer insertion. These are the techniques to improve power dissipation, area usage, noise and time delay. The interconnect delay can be optimized by choosing proper buffer locations along the routing path. A stochastic based Particle Swarm Optimization algorithm is used here to optimize buffer locations to find the shortest path and also simultaneously minimize the congestion. The performance is compared with Particle Swarm Optimization based VLSI routing. The results obtained shows the proposed approach has a good potential in VLSI routing and can be further extended in future.