Single Electron Encoded Logic Full Adder

To ability to control the transport of individual electrons in Single Electron Tunneling (SET) based circuits creates the conditions for Single Electron Encoded Logic (SEEL). This paper involves the implementation of full adder using SEEL elements. In SEEL the designing of linear equations for a specific logic circuit with the representation of positive, negative weights and desired threshold value can be implemented with a single electron box. The concept of SEEL realizes the logic behaviour by controlling the capacitance of bias for adjusting the gate threshold to realise the desired logic with inverting or non-inverting buffer. The re-configurability of gates is done by varying the bias capacitance. After introduction of the threshold gate and buffer/inverter, which serve as basic circuit blocks, SEEL implementations as the full adder are proposed and verified by simulation. Finally, the area, switching delay, speed power product and power consumption of the elements are compared with SEEL 1-bit full adder to n-bit adder.