Power Optimized Embedded Processor Design with Parallel Pipelining

Power has become an important aspect in the design of general purpose processors. Hence, to explore how design tradeoffs affect the power and performance of the processor. Proper implementation of pipelining structure at the architectural level may consume less power and help to improve the energy efficiency of the processor, and may dissipate less power for the same performance or higher performance for the same power. Some architectural changes, such as pipelining and caching, can significantly improve efficiency. Unfortunately many other architectural tradeoffs leave efficiency unchanged. This is because a large fraction of the energy is dissipated in essential functions and is unaffected by the internal organization of the processor. This paper discusses the design and implementation of power optimized parallel pipelined structures of 16-bit CPU on Xilinx Spartan-3E FPGA. A modified processor architecture is proposed to reduce the unnecessary switching activities to achieve significant power reduction.