A High Throughput VLSI Architecture Using Sphere Decoder Algorithm for Wireless Applications

Multiple Input Multiple Output (MIMO) system is regarded as a promising solution to offer ultra-high data rate in wireless communications. The use of multiple antennas at both transmitter and receiver (MIMO) significantly increases the capacity and spectral efficiency of wireless systems. This paper presents a Field Programmable Gate Array (FPGA) implementation for a 4×4 breadth first K-best MIMO decoder using a 64 Quadrature Amplitude Modulation (QAM) scheme. A novel sort free approach to path extension, as well as, quantized metrics result in a high throughput, low power and area. Finally, VLSI architectural tradeoffs are explored for a synthesized using synopsys the power analysis, throughput analysis in 120nm technology.